The present invention relates to semiconductor devices and, more specifically, to fabrication method and resulting structures for an interlayer via with a double spacer and sidewall contacts.
In semiconductor device manufacturing, three dimensional (3D) monolithic designs often use stacked layers of devices that are sequentially processed to reduce a device footprint. In such cases and especially for devices with p-type field effect transistors (FETs) over n-type FETs or vice versa, there needs to be a significant number of interlayer vias provided to make a functional circuit. Such interlayer vias can consume a large amount of surface area and thereby diminish scaling benefits of this approach.